Panasonic FPG-COM2-A - Page 144

FPΣ User's Manual
7.4 Pulse Output Function
127
Resetting the elapsed value (software reset) of the high-speed counter to 0
01
0
t
2
Y*
1
Y* Pulse output
1
Elapsed value
2
Bit 0 of pulse output control code (software reset)
When bit 0 of the control code is set to TRUE, a software reset is performed and the elapsed
value is set to 0. The elapsed value keeps the value 0 until bit 0 is reset to FALSE.
Control code settings
Bits 0–15 of the control code are allocated in groups of four. The bit setting in each group is
represented by a hex number (e.g. 0002 0001 0000 1001 = 16#2109).
15 12 11 8 7 4 3 0

IIIIIIIV

Group IV
1
Channel number (channel n: 16#n)
Group III 0 (fixed)
Near home input (bit 4)
Group II
2
0: FALSE 1: TRUE
Pulse output (bit 3)
3
0: continue 1: stop
4
0 (bit 2, fixed)
Count (bit 1)
5
0: permit 1: prohibit
Reset elapsed value to 0 (bit 0)
Group I
6
0: no 1: yes