Panasonic TH-103PF9EK - DN-Board (2 of 3) Block Diagram

13.19. DN-Board (2 of 3) Block Diagram
P3V_SCL2
P3V_SCL2
P3V_SDA2
P3V_SDA2
P3V_SCL3
P3V_SDA3
P3V_SDA2 P3V_SCL2
STB+3.3V
+3.3V
+1.5V +2.5V
+3.3V
+1.5V
+3.3V
STB+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+2.5V
+3.3V
+3.3V
MCCLK
PORT1_HS,_VS,_CLK
8
PORT1_ROUT0-9
2
[ODD]
A0-A18
26
BUFFER
2
XT
BO0-9
1
FPGA3 OUTPUT
RO0-9
SD RAM2 DATA
XTN
GO0-9
20
DDR-SDRAM I/F
HDO,VDO,CLKO
4
DQ0-DQ31
PORT1_GOUT0-9
6
PORT1_BOUT0-9
FPGA_DATA0
7
ADDR0-11
5
FPGA_NSTATUS
CPLD(FPGA ROM)
FLD
DQ1-DQ31
(90MHz)
LCLK1
FPGA_NCONFIG
CLK2X_E
OSD_72MHz
SDAT
PORT2_ROUTE0-9
ICHIPS-RST
7
RE0-9
PORT2_GOUTE0-9
(30bit)
HDE,VDE,CLKE-57
RVIA0-9
FLASH
(30bit)
BUIA0-9
DATA0-15
DEV-OE
POCLK
FLASH
MCLK
LSI57Plus
GOUT0-9
RGB OUT
IC4906
RV,GY,BU
BOUT0-9
SD-RAM
VCC
IC4501
XIN
X2CBCLK_A
SD-RAM1 DATA
1
SO
1
LCLK2
FPGA_BINE0-9
SI
8
FPGA_RINE0-9
PI1CLK
FPGA_GINE0-9
WE,CE,OE
PI1FLD,PI1ACTB
FPGA_HDE,VDE,CLKE
REFCK
CONFIG-OE
CLKM_20MHz
OCKREF
ADDR0-18
CLK7425
P1_Y/G0-9
NWE,NCE,NOE
P1_PR/R0-9
LSI57-HP,-VP,-CLK
8M FLASH MEMORY
IIC_BUS
IC4902
CLK3
14
57_R0-9
DQ1-DQ15
(39.5MHz)
RESET
CLK4
57_B0-9
WE,CE,OE
LSI57_GIN0-9
VCC
IC5103
BE0-9
LSI57 INPUT
12
8
GE0-9
CLK6
NRST
OE1
TDO
D0,D5-D7,D12-D15
X5701
TDI
PORT1_FLD,_ACT
SD_RAM2
ADDR0-11
PORT2_BOUTE0-9
VCC
IC5503
DQ1-DQ31
VDD
LCLK2
P1_FLD,_ACT
WE,CAS,RAS
32M DDR SDRAM
CBCLK_A
RVIB0-9
P2_Y/GO0-9
FPGA2
(4.25MHz)
1
BUIB0-9
IC5201
CLK7
FPGA-TMS
XIN
SCLKB
VCC
7
FPGA-TCK
RSTB
I-CHIPS PORT1 OUTPUT
CPG
4
IC5701
RGB IN PORT2
POHSB,POVSB
8
(60bit)
RESET
POFLD,POAVTB
IIC_BUS
7
IIC_CLK
CLKM_20MHz
NRST-FP
(74.25MHz)
OSD_72MHz
ADDRESS
9
BUFFER
POD_0-POD_59
BUFFER
FPGA_FLD
(72MHz)
CLK2X_E
13
FPGA_DCLK
SCLK
P2_PR/RE0-9
FPGA_DCLK
1
6
VCC
RGB IN PORT1
P1_PB/B0-9
5
IC4908
P1_HS,_VS,_CLK
3
CLOCK BUFFER
PI2HSB,PI2VSB,
CLK5
IC5103
PI2CLK
OCK_90MHz
10
24
11
CLK INPUT
23
IC4904
9
CPU I/F
22
FPGA-TDI
FPGA_DCLK
GCLK2
FPGA_DCLK
IC4302
FACTORY USE
GYIB0-9
2
DHB,DVB,
DCKB
(FPGA ROM WRITER)
I-CHIPS PORT2 OUTPUT
(30bit)
PORT2_GOUTO0-9
FPGA_DATA0
I-CHIPS
FPGA_NSTATUS
GYIA0-9
BUFFER
IIC_SDA
DHA,DVA,
DCKA
(30bit)
BUFFER
IIC_SCL
[EVEN]
[EVEN]
FPGA_BINO0-9
PO_HS,_VS
VDD
[ODD]
GND
[ODD]
FPGA_RINO0-9
PO_RO0-9,PO_GO0-9,PO_BO0-9
8
IC4903
3
SD_RAM1
PORT2_BOUTO0-9
DN
10
VCC
WE,CAS,RAS
PORT2_ROUTO0-9
SCLK
FOR
IIC_BUS
NRST
DIR
OE1
REFCK_39.5MHz
IC4907
SCKREF
PO_CLK
OE1
FPGA-TDO
MCKREF
CLK2
VCC
X2CBCLK_B
5
OCK-90MHz
(40MHz)
VCC
FPGA_GINO0-9
5
FPGA1 INPUT
DIR
FPGA_HDO,VDO,CLKO
VCC
A0-A2,A16,A19,CE2,OE
IC5502
REFCK39.5MHz
A3-A7,A17,A18WE
CLK7425-1
PI1DO_0-PI1D_29
IC5501
VCC
PI1HSB,PI1VSB,
INTERFACE
21
IC4905
25
27
RESET
1
FPGA_CONFDONE
NRST
FPGA_CONFDONE
VOUT
[EVEN]
IIC_SDA
VDD
IIC_SCL
CONFIGURATION
TMS
FPGA_NCONFIG
P2_PR/RO0-9
TCK
PI2DO_0-PI2D_29
6
P2_FLD,_ACT
HP,VP,OCKO
PI2FLD,PI2ACTB
CLOCK BUFFER
ROUT0-9
LSI57_RIN0-9
OSD_CLKO
P2_HS,_VS,_CLK
P2_PB/BE0-9
LSI57_BIN0-9
PORT2_FLD,_ACT
OSD_CLKI
ADRS0-ADRS11
P2_PB/BO0-9
P2_Y/GE0-9
PORT2_HS,_VS,_CLK
CBCLK_B
PO_FLD,_ACT
I2CSDA
IC4502
CLK1
LCLK1
PO_RE0-9,PO_GE0-9,PO_BE0-9
I2CSCL
57_G0-9
(2088MHz)
(60bit)
57_HD,57_VD,57_CLK
SDAT
MC D ATA- 0
D1-D4,D8-D11
D1-D15
IIC_BUS
ICHIPS-SI
A8-A15
A0-A18
DN
DIGITAL SIGNAL PROCESSOR/MICOM
(Exchange board only)
!
<TZTNP01YLTU>
TH-103PF9UK/EK
DN-Board (2 of 3) Block Diagram
TH-103PF9UK/EK
DN-Board (2 of 3) Block Diagram
TH-103PF9UK / TH-103PF9EK
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