Radstone PowerPact - J2 Connector Pinout

PowerPact6 Processors Family Product Manual
Standard Interfaces
1
st
Edition 5-5
J2 Connector Pinout
PIN ROW A ROW B ROW C ROW D ROW E ROW F
22 GA4 GA3 GA2 GA1 GA0 GND
21 CLK6 GND No Connection No Connection No Connection GND
20 CLK5 GND No Connection GND No Connection GND
19 GND GND No Connection No Connection No Connection GND
18 No Connection No Connection No Connection GND No Connection GND
17 No Connection GND RST~ REQ6~ GNT6~ GND
16 No Connection No Connection DEG~ GND No Connection GND
15 No Connection GND FAL~ REQ5~ GNT5~ GND
14 AD(35) AD(34) AD(33) GND AD(32) GND
13 AD(38) GND V(IO) AD(37) AD(36) GND
12 AD(42) AD(41) AD(40) GND AD(39) GND
11 AD(45) GND V(IO) AD(44) AD(43) GND
10 AD(49) AD(48) AD(47) GND AD(46) GND
9 AD(52) GND V(IO) AD(51) AD(50) GND
8 AD(56) AD(55) AD(54) GND AD(53) GND
7 AD(59) GND V(IO) AD(58) AD(57) GND
6 AD(63) AD(62) AD(61) GND AD(60) GND
5 CBE(5) 64EN~ V(IO) CBE(4)~ PAR64 GND
4 V(IO) No Connection CBE(7)~ GND CBE(6)~ GND
3 CLK4 GND GNT3~ REQ4~ GNT4~ GND
2 CLK2 CLK3 SYSEN~ GNT2~ REQ3~ GND
1 CLK1 GND REQ1~ GNT1~ REQ2~ GND
" CAUTION
For optimum performance, PowerPact6 processors have been designed for use with 64-bit
CompactPCI backplanes. They may also be used with 32-bit backplanes, but with a
corresponding performance loss.