1
st
Edition 5-11
J14 (User I/O) Connector Pinout
J14 is mapped to the J5 backplane connector
as follows:
J24 (User I/O) Connector Pinout
J24 is mapped to the J3 backplane connector
as follows:
J14 PIN J5 PIN J14 PIN J5 PIN J24 PIN J3 PIN J24 PIN J3 PIN
1 E22 2 D22 1 E13 2 D13
3 C22 4 B22 3 C13 4 B13
5 A22 6 E21 5 A13 6 E12
7 D21 8 C21 7 D12 8 C12
9 B21 10 A21 9 B12 10 A12
11 E20 12 D20 11 E11 12 D11
13 C20 14 B20 13 C11 14 B11
15 A20 16 E19 15 A11 16 E10
17 D19 18 C19 17 D10 18 C10
19 B19 20 A19 19 B10 20 A10
21 E18 22 D18 21 E9 22 D9
23 C18 24 B18 23 C9 24 B9
25 A18 26 E17 25 A9 26 E8
27 D17 28 C17 27 D8 28 C8
29 B17 30 A17 29 B8 30 A8
31 E16 32 D16 31 E7 32 D7
33 C16 34 B16 33 C7 34 B7
35 A16 36 E15 35 A7 36 E6
37 D15 38 C15 37 D6 38 C6
39 B15 40 A15 39 B6 40 A6
41 E14 42 D14 41 E5 42 D5
43 C14 44 B14 43 C5 44 B5
45 A14 46 E13 45 A5 46 E4
47 D13 48 C13 47 D4 48 C4
49 B13 50 A13 49 B4 50 A4
51 E12 52 D12 51 E3 52 D3
53 C12 54 B12 53 C3 54 B3
55 A12 56 E11 55 A3 56 E2
57 D11 58 C11 57 D2 58 C2
59 B11 60 A11 59 B2 60 A2
61 E10 62 D10 61 E1 62 D1
63 C10 64 B10 63 C1 64 B1
$
Note: The PowerPact6 processors do not implement the additional signals defined by VITA32 (Processor PMC
Standard).
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