ROHS MC9S08QE128 - Page 14

MC9S08QE128 MCU Series Reference Manual, Rev. 2
Freescale Semiconductor 15
Section Number Title Page
12.3.6 IIC Control Register 2 (IICxC2) .....................................................................................227
12.4 Functional Description ..................................................................................................................228
12.4.1 IIC Protocol .....................................................................................................................228
12.4.2 10-bit Address .................................................................................................................232
12.4.3 General Call Address ......................................................................................................233
12.5 Resets ............................................................................................................................................233
12.6 Interrupts .......................................................................................................................................233
12.6.1 Byte Transfer Interrupt ....................................................................................................233
12.6.2 Address Detect Interrupt .................................................................................................233
12.6.3 Arbitration Lost Interrupt ................................................................................................233
12.7 Initialization/Application Information ..........................................................................................235
Chapter 13
Real-Time Counter (S08RTCV1)
13.1 Introduction ...................................................................................................................................237
13.1.1 ADC Hardware Trigger ..................................................................................................237
13.1.2 RTC Clock Sources .........................................................................................................237
13.1.3 RTC Modes of Operation ................................................................................................237
13.1.4 RTC Clock Gating ...........................................................................................................237
13.1.5 Interrupt Vector ...............................................................................................................238
13.1.6 Features ...........................................................................................................................240
13.1.7 Modes of Operation ........................................................................................................240
13.1.8 Block Diagram ................................................................................................................241
13.2 External Signal Description ..........................................................................................................241
13.3 Register Definition ........................................................................................................................241
13.3.1 RTC Status and Control Register (RTCSC) ....................................................................242
13.3.2 RTC Counter Register (RTCCNT) ..................................................................................243
13.3.3 RTC Modulo Register (RTCMOD) ................................................................................243
13.4 Functional Description ..................................................................................................................244
13.4.1 RTC Operation Example .................................................................................................245
13.5 Initialization/Application Information ..........................................................................................245
Chapter 14
Serial Communications Interface (S08SCIV4)
14.1 Introduction ...................................................................................................................................247
14.1.1 SCI Clock Gating ............................................................................................................247
14.1.2 Interrupt Vectors ..............................................................................................................247
14.1.3 Features ...........................................................................................................................250
14.1.4 Modes of Operation ........................................................................................................250
14.1.5 Block Diagram ................................................................................................................251
14.2 Register Definition ........................................................................................................................253
14.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ..........................................................253