ROHS MC9S08QE128 - Page 76

Chapter 4 Memory
MC9S08QE128 MCU Series Reference Manual, Rev. 2
76 Freescale Semiconductor
4.6.2.6 Flash Command Register (FCMD)
The FCMD register is the flash command register.
All FCMD bits are readable and writable during a command write sequence while bit 7 reads 0 and is not
writable.
4
FACCERR
Flash Access Error Flag — The FACCERR flag indicates an illegal access has occurred to the flash memory
or flash IFR caused by either a violation of the command write sequence (see Section 4.6.3.1.2, “Command
Write Sequence”), issuing an illegal flash command (see Table 4-21), or the execution of a CPU STOP instruction
while a command is executing (FCCF = 0). Writing a 0 to the FACCERR flag has no effect on FACCERR. The
FACCERR flag is cleared by writing a 1 to FACCERR.While FACCERR is set, it is not possible to launch a
command or start a command write sequence.
0 No access error detected.
1 Access error has occurred.
2
FBLANK
Flash Flag Indicating the Erase Verify Operation Status — When the FCCF flag is set after completion of an
erase verify command, the FBLANK flag indicates the result of the erase verify operation. The FBLANK flag is
cleared by the flash module when FCBEF is cleared as part of a new valid command write sequence. Writing to
the FBLANK flag has no effect on FBLANK.
0 Flash block verified as not erased.
1 Flash block verified as erased.
76543210
R0
FCMD
W
Reset 00000000
= Unimplemented or Reserved
Figure 4-15. Flash Command Register (FCMD)
Table 4-20. FCMD Field Descriptions
Field Description
6:0
FCMD[6:0]
Flash Command — Valid flash commands are shown in Table 4-21. Writing any command other than those
listed in Table 4-21 sets the FACCERR flag in the FSTAT register.
Table 4-21. Valid Flash Command List
FCMD[6:0] NVM Command
0x05 Erase Verify
0x20 Program
0x25 Burst Program
0x40 Sector Erase
0x41 Mass Erase
Table 4-19. FSTAT Field Descriptions
Field Description