Samsung ML-451 Series - 5.5. Connection Diagram 4

5.SystemDiagrams
5.5.ConnectionDiagram4
BLDC
DEVE
BLDC
MAIN
BLDC
MT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
BLDC_ DE VE_ DIR
BLDC_DEVE_C LK
n B LDC _ DE VE_ R EADY
BLDC_DEVE_E N
BLDC_ DE VE_ G AIN
BLDC_DEVE_B R AKE
DGND
DGND
24VS 1
24VS 1
BLDC_ MAIN_DIR
BLDC_ MAIN_CLK
n B LDC _ MAIN_READY
BLDC_MAIN_EN
5VP
BLDC_ MAIN_BRAKE
DGND
DGND
24VS 1
24VS 1
CN 12
BLDC (1.5 m m )
MT
Ela va tin g DC mo to r
CC W
1
2
3
4
5
6
7
8
CS T_ O P EN
P _ S IZE3
P _ S IZE2
DGND
P _ S IZE1
(NC)
ELEV_S W_ O N(24 V)
EN_ E LE V_MOT
CN 19
CS T & ELE V MOT (1 .5m m )
1
2
3
4
3.3V
DEBUG_TXD
DEBUG_R XD
DGND
CN 21
DEB UG G E R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DGND
1. 8V
MDIP3
MDIN3
MDIP2
MDIN2
MDIP1
MDIN1
MDIP0
MDIN0
3. 3V
LED1
3. 3V
LED0
FG ND
FG ND
CN 16
GIGABIT ETHE RNET(RJ -45)
1
2
3
4
5
6
7
8
3.3V
TDO
n TRS T
TCK
TMS
TDI
n RES ET
DGND
CN 27
J TAG
1
2
3
4
5
6
VBUS _ R E AR _HO S T
DN_REAR_ HO S T
DP _REAR_HOS T
DGND
FG ND
FG ND
CN 5
RE AR US B HOS T I/F(FDI)
1
2
3
4
5
6
VBUS _ C 4 _DEVICE
DN_C4_ DE VICE
DP _C4_DEVICE
DGND
FG ND
FG ND
CN 2
UBS DEVICE
1
2
3
4
5
6
7
8
9
DGND
S ATA_TX_P
S ATA_TX_N
DGND
S ATA_R X_N
S ATA_R X_P
DGND
DGND
DGND
CN 23
S ATA S IGNAL (4 8 On ly)
1
2
5V
DGND
CN 24
SATA P OWER (2.0m m )
(48 On ly)
10
9
8
7
6
5
4
3
2
1
CW/CC W
CLK
RE ADY
S S
+5V
BR AKE
P G ND
P G ND
+24V
+24V
P AP ER S IZE MODULE
(NEW, Ha r r ie r) J C34-000 01A
1
2
1
2
3
4
5V
(N.C)
DGND
DGND
CN 31
J AC K DC-P O WE R
PARALLEL OP TION
BLDC
MT
10
9
8
7
6
5
4
3
2
1
CW/CC W
CLK
RE ADY
SS
+5V
BR AKE
PG ND
PG ND
+24V
+24V
Main board
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