Schweitzer Engineering Laboratories SEL-251 - IRIG-B Input Description; Signal Processing; Table 2.5: Self-Test Summary

Date Code 20000421 Specifications 2-25
SEL-251, -2, -3 Instruction Manual
Table 2.5: Self-Test Summary
Self-Test Limits
Status
Message
Protection
Disabled
Control
Disabled
Alarm
Output
RAM ---- F YES YES permanent contact assertion
ROM ---- F YES YES permanent contact assertion
SETTINGS ---- F YES YES permanent contact assertion
A/D ---- F YES NO permanent contact assertion
+5 V ±0.3 V
±0.4 V
W
F
NO
YES
NO
YES
no ALARM contact assertion
permanent contact assertion
±15 V ±0.8 V
±1.2 V
W
F
NO
YES
NO
NO
no ALARM contact assertion
permanent contact assertion
CHANNEL
OFFSETS
50 mV
75 mV
W
F
NO
NO
NO
NO
no ALARM contact assertion
one second contact pulse
MASTER
OFFSET
50 mV
75 mV
W
F
NO
NO
NO
NO
no ALARM contact assertion
one second contact pulse
IRIG-B INPUT DESCRIPTION
The port labeled J201/AUX INPUT receives demodulated IRIG-B time code input. The IRIG-B
input circuit is a 56 ohm resistor in series with an opto-coupler input diode. The input diode has
a forward drop of about 1.5 volts. Driver circuits should put approximately 10 mA through the
diode when "on."
On the plug-in connector model, Ports 1 and 2R may be configured to accept demodulated
IRIG-B input. When JMP 13 and JMP 14 are bridged, pins 6 and 4 will accept -IRIG-B and
+IRIG-B, respectively. See Table 3.2 for port pinouts.
The IRIG-B serial data format consists of a one second frame containing 100 pulses and divided
into fields. The relay decodes second, minute, hour, month, and day fields and sets the relay
clock accordingly.
When IRIG-B data acquisition is activated either manually (with the IRIG command) or auto-
matically, the relay reads two consecutive frames. It updates the older frame by one second and
compares the frames. If they do not agree, the relay considers the data erroneous and discards it.
The relay reads the time code automatically about once every five minutes. It stops IRIG-B data
acquisition ten minutes before midnight on New Year's Eve so the relay clock can implement the
year change without interference from the IRIG-B clock.
SIGNAL PROCESSING
The relay low-pass filters all analog input channels to remove high frequency components. Next
it samples each channel four times per power system cycle. After low-pass filtering, the relay
digitally filters each sample with the CAL digital filter method. The CAL filter eliminates dc
offset and reduces the decaying exponential offset that may be present on the input signal fol-
lowing a fault.