General-purpose timers (TIM15/TIM16/TIM17) RM0440
1380/2126 RM0440 Rev 4
They allow to have:
• A board-level global break signal available for signaling faults to external MCUs or gate
drivers, with a unique pin being both an input and an output status pin
• Internal break sources and multiple external open drain sources ORed together to
trigger a unique break event, when multiple internal and external break sources must
be merged
The tim_brk input is configured in bidirectional mode using the BKBID bit in the TIMxBDTR
register. The BKBID programming bit can be locked in read-only mode using the LOCK bits
in the TIMxBDTR register (in LOCK level 1 or above).
The bidirectional mode requires the I/O to be configured in open-drain mode with active low
polarity (using BKINP and BKP bits). Any break request coming either from system (e.g.
CSS), from on-chip peripherals or from break inputs forces a low level on the break input to
signal the fault event. The bidirectional mode is inhibited if the polarity bits are not correctly
set (active high polarity), for safety purposes.
The break software event (triggered by setting the BG bit) also causes the break I/O to be
forced to '0' to indicate to the external components that the timer has entered in break state.
However, this is valid only if the break is enabled (BKE = 1). When a software break event is
generated with BKE = 0, the outputs are put in safe state and the break flag is set, but there
is no effect on the TIM_BKIN I/O.
A safe disarming mechanism prevents the system to be definitively locked-up (a low level on
the break input triggers a break which enforces a low level on the same input).
When the BKDSRM bit is set to 1, this releases the break output to clear a fault signal and to
give the possibility to re-arm the system.
At no point the break protection circuitry can be disabled:
• The break input path is always active: a break event will be active even if the BKDSRM
bit is set and the open drain control is released. This will prevent the PWM output to be
re-started as long as the break condition is present.
• The BKDSRM bit cannot disarm the break protection as long as the outputs are
enabled (MOE bit is set) (see Table 295)
Arming and re-arming break circuitry
The break circuitry (in input or bidirectional mode) is armed by default (peripheral reset
configuration).
Table 295. Break protection disarming conditions
MOE BKBID BKDSRM Break protection state
0 0 X Armed
0 1 0 Armed
0 1 1 Disarmed
1 X X Armed
To Next Page
Loading...
Need help?
General
