RM0440 Rev 4 487/2126
RM0440 Filter math accelerator (FMAC)
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18.3 FMAC functional description
18.3.1 General description
The FMAC is shown in Figure 41.
Figure 41. Block diagram
The unit is built around a fixed point multiplier and accumulator (MAC). The MAC can take
two 16-bit input signed values from memory, multiply them together and add them to the
contents of the accumulator. The address of the input values in memory is determined using
a set of pointers. These pointers can be loaded, incremented, decremented or reset by the
internal hardware. The pointer and MAC operations are controlled by a built-in sequencer in
order to execute the requested operation.
To calculate a dot product, the two input vectors are loaded into the local memory by the
processor or DMA controller, and the requested operation is selected and started. Each pair
of input vector elements is fetched from memory, multiplied together and accumulated.
When all the vector elements have been processed, the contents of the accumulator are
stored in the local memory, from where they can be read out by the processor or DMA.
The finite impulse response (FIR) filter operation (also known as convolution) consists in
repeatedly calculating the dot product of the coefficient vector and a vector of input samples,
the latter being shifted by one sample delay, with the least recent sample being discarded
and a new sample added, at each repetition.
The infinite impulse response (IIR) filter operation is the convolution of the feedback
coefficients with the previous output samples, added to the result of the FIR convolution.
A more detailed description of the filter operations is given in Section 18.3.6: Filter functions.
Local
Memory
Multiply and
Accumulate
(MAC)
Read
pointer
Write
pointers
Buffer base
address
pointers
Buffer size
registers
AHB interface
x1, x2
offset
pointers
y offset
pointers
Control and sequencing
AHB
MSv45868V1
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