System configuration controller (SYSCFG) RM0440
370/2126 RM0440 Rev 4
Note: When the FSMC is remapped at address 0x0000 0000, only the first two regions of Bank 1
memory controller (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) can be remapped. In remap
mode, the CPU can access the external memory via ICode bus instead of System bus
which boosts up the performance.
10.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1)
Address offset: 0x04
Reset value: 0x7C00 0001
Bits 2:0 MEM_MODE: Memory mapping selection
These bits control the memory internal mapping at address 0x0000 0000. These bits are
used to select the physical remap by software and so, bypass the BOOT pin and the option
bit setting. After reset these bits take the value selected by BOOT0 pin (or option
bitnSWBOOT0) and BOOT1 option bit.
000: Main Flash memory mapped at 0x00000000
(1)
.
001: System Flash memory mapped at 0x00000000.
010: FSMC memory.
011: SRAM1 mapped at 0x00000000.
100: QUADSPI memory mapped at 0x0000 0000
101: Reserved
111: Reserved
1. When BFB2 bit is set, the system memory remains aliased at @0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FPU_IE[5..0] Res Res
I2C4_
FMP
I2C3_
FMP
I2C2_
FMP
I2C1_
FMP
I2C_
PB9_
FMP
I2C_
PB8_
FMP
I2C_
PB7_
FMP
I2C_
PB6_
FMP
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Res Res Res Res Res Res
ANAS
WVDD
BOOST
EN
Res Res Res Res Res Res Res Res
rw rw
Bits 31:26 FPU_IE[5..0]: Floating Point Unit interrupts enable bits
FPU_IE[5]: Inexact interrupt enable
FPU_IE[4]: Input denormal interrupt enable
FPU_IE[3]: Overflow interrupt enable
FPU_IE[2]: underflow interrupt enable
FPU_IE[1]: Divide-by-zero interrupt enable
FPU_IE[0]: Invalid operation interrupt enable
Bits 25:24 Reserved, must be kept at reset value.
Bit 23 I2C4_FMP: Fast-mode Plus driving capability activation
This bit enables the Fm+ driving mode on I2C4 pins selected through AF selection bits.
0: Fm+ mode is not enabled on I2C4 pins selected through AF selection bits
1: Fm+ mode is enabled on I2C4 pins selected through AF selection bits.
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