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TB8100 Service Manual Reciter Circuit Description 35

The Rx Gate and Tx Relay lines go via the system interface board for signal

conditioning.

2.1.4 40MHz Digital Clock

The 40MHz synthesized digital clock is situated on the digital board. It is

used to drive the entire digital circuitry.

The 40MHz frequency synthesizer is implemented using an Integer_N-

based phase locked loop (PLL) IC. The PLL is a negative feedback loop,

which continuously monitors and maintains the 40MHz VCXO to a fixed

frequency and constant phase relationship with respect to a 12.8MHz

reference. The 40MHz VCXO oscillator is electrically tuned using two

varactors. The oscillator output is buffered before being distributed to the

digital circuitry.

2.2 Reference Switch

Refer to Figure 2.4 on page 37.

2.2.1 Synthesizer

The external reference synthesizer consists of a programmable frequency

synthesizer IC, a 12.8MHz VCXO, and a stable 10MHz or 12.8MHz

reference frequency supplied to the reciter externally via a BNC connector

on the rear panel.

The synthesizer uses a phase-locked loop to lock the 12.8MHz VCXO to

the external reference frequency. The synthesizer IC receives the divider

and control information from the RISC processor via a 3-wire serial bus

(clock, data and enable). When the data bits are latched in, the synthesizer

processes incoming signals from the 12.8MHz VCXO feedback buffer

vcxofb

) and the external reference buffer (f

ref

A transistor is used as a unity gain 12.8MHz VCXO feedback buffer for the

prescaler within the synthesizer IC.

The 10MHz or 12.8MHz externally supplied reference is detected, buffered

and divided down to the 100kHz divider reference within the synthesizer

IC. The same divider reference is maintained by dividing the 12.8MHz

VCXO feedback buffered signal using the programmable dividers of the

synthesizer IC. Phase lock is achieved when both divider references have

the same phase and frequency content (i.e. their difference is zero or DC).

This is achieved by the digital phase detector (part of the synthesizer IC),

which compares both divider references and delivers an error signal. A

±1mA charge pump circuit (also part of the synthesizer IC) and the passive

loop filter circuit convert this error signal to a DC voltage (0 to 3V) to tune

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