Tait TP9100 - Page 174

174 Frequency Synthesizer Fault Finding TP9100 Service Manual
© Tait Electronics Limited May 2005
Task 10 —
SYN LOCK Line
If all the critical inputs to the PLL are correct, check the SYN LOCK line
output.
1. Enter the CCTM command 72 to determine the lock status in receive
mode. Note the status.
2. Check the
SYN LOCK line by measuring the voltage at pin 14 of IC503
(see Figure 9.3). The voltage should depend on the lock status as
follows:
3. If the voltage measured in Step 2 is correct, go to “Loop Filter” on
page 176. If it is not, go to Step 4.
4. Check for continuity between pin 14 of IC503 and the digital input
R742 to D1 of IC701 (
DIG TOP can) (Figure 9.7).
5. If there is a fault, go to Step 6. If there is no fault, the digital circuitry
is faulty; replace the main board, and go to “Final Tasks” on
page 134.
6. Repair the fault. Confirm the removal of the fault and go to “Final
Tasks” on page 134. If the repair failed or no fault could be found,
replace the main board, and go to “Final Tasks” on page 134.
lock status=xyz (x=RF PLL; y=FCL; z=LO2) (0=not in lock; 1=in lock)
lock status 111 or 110: 3.0 ± 0.3V DC at pin 14 of IC503
lock status 011 or 010: 0V DC at pin 14 of IC503