46 Description TP9100 Service Manual
© Tait Electronics Limited May 2005
Frequency
Acquisition of
RF PLL
In the RF PLL the loop bandwidth is initially set to high by increasing the
charge-pump current and reducing time constants in the loop filter.
As a result, settling to within 1kHz of the final value occurs in under 4ms.
In order to meet noise performance requirements the loop parameters are
then switched to reduce the loop bandwidth. There is a small frequency kick
as the loop bandwidth is reduced. Total settling time is under 4.5ms.
Frequency
Acquisition of FCL
The FCL utilizes self-calibration techniques that enable it to rapidly settle
close to the final value while the loop is open. The loop is then closed and
settling to the final value occurs with an associated reduction in noise.
The total settling time is typically less than 4ms.
Calibration The following items are calibrated in the frequency synthesizer:
■ nominal frequency
■ KVCO
■ KVCXO
■ VCO deviation
Calibration of the nominal frequency is achieved by adding a fixed offset to
the FCL nominal frequency; the TCXO frequency itself is not adjusted.
The items KVCO and KVCXO are the control sensitivities of the RF VCO
(in MHz/V) and VCXO (in kHz/V) respectively. The latter has
temperature compensation.
2.6.3 RF Transmitter
RF Power Amplifier
and Switching
The RF power amplifier is a four-stage line-up with approximately 32dB of
power gain. The output of the frequency generation sub-system is first
buffered to reduce kick during power ramping. The buffer output goes to
an exciter IC that produces approximately 100mW output. This is followed
by an LDMOS driver producing up to 1.5W output that is power-
controlled. The final stage consists of a single LDMOS device producing up
to 4W for UHF and 5W for VHF.
Output of RF Power
Amplifier
The PIN switch toggles the antenna path between the receiver and
transmitter in receive and transmit modes respectively. Finally, the output is
low-pass-filtered to bring harmonic levels within specification.