Tait TP9100 - Page 55

TP9100 Service Manual Circuit Descriptions 55
© Tait Electronics Limited May 2005
Automatic Gain
Control
The receiver has an AGC circuit to enable it to cover a large signal range.
Most of the circuit functions are implemented in the FPGA. The FPGA
passes the AGC signal to the CODEC IC204 for output from pin 14
(
IDACOUT) and thence via IC201 as the signal CDC TXFIN RXAGC to pin 23 of the
quadrature mixer IC400. As the antenna signal increases, the AGC voltage
decreases.
Channel Filtering The channel filtering is split between the first and third IF stages.
The channel filtering circuit in the first IF stage comprises a pair of two-pole
crystal filters. The first filter has a 3dB bandwidth of 12kHz, and the second
a 3dB bandwidth of 15kHz. Most of the channel filtering, however, is
implemented in the FPGA and the DSP. When the radio is programmed,
the different filters are selected as assigned by the channel programming.
The selectable filters plus the fixed crystal filters result in the following total
IF 3dB bandwidths:
■ wide channel spacing : 12.6kHz
■ medium channel spacing: 12.0kHz
■ narrow channel spacing : 7.8kHz
(The FPGA runs from the
FPGA 24M576 CLK signal, which has a frequency of
24.576MHz.) The receiver requires the TCXO calibration to be completed
to ensure that the channel filtering is centered, thereby minimizing
distortion.
Received Signal
Strength Indication
The RSSI is calculated in the FPGA and DSP. To obtain an accurate
estimate of the RSSI (over the signal level and frequency), it is necessary to
calibrate the AGC characteristic of the receiver and the front-end gain versus
the receive frequency.