Theory of operation
Each LTC signal
is switched with a double-pole relay. The unused input is not
terminated. Each input has a level detector to drive the front-panel status LEDs
and the ECO switching logic. Each Channel has a DAC to set the threshold for
the fault detection.
GPIO and Expansion ports
The GPIO and Expansion ports on the Main board are basically interfaces to the
PLD pins. The Expansion port can either drive or receive on each line, which
allows each instrume nt to be configured either as a master or as a slave. Use a 1-1
RJ45 Ethernet-style cable to connect two instruments.
Processo
r board
The Processor monitors the right-hand keys (Configuration and Monitoring
system) and drives the LCD, which together implement the loca l UI. The Processor
isasmal
l ARM-style running a Linux OS. It has NOR flash to store the program,
DDR2 for program execution, and MRAM to store settings. The Processor also
has a real time clock to provide time stamps for the log, and an Ethernet interface
to provide remote configuration and monitoring. The Processor board uses the
raw 5.25 V supply from the Main board and generates all the supplies it needs for
the Processor functions with an integrated power management chip.
The Processor has two status LEDs (DS1 and DS2). DS1 is a heartbeat LED;
it blinks if the P rocessor is running the normal application. If the b link rate is
slow
er than 2-3 per socond, that indicates excessive loading on the Processor.
DS2 indicates the 3.3 VA is present out of the power management chip.
The
Processor uses I2C to communicate with the redundant power system on the
Combiner board and Power Supply modules, and uses SPI to communicate with
the channel control system on the Main board and Channel modules.
For SPI, the Processor b oard generates six separate chip selects to allow it to talk
to the Main board PLD, each Channel module PLD, or the voltage monitor. The
other SPI signals are buffered on the Main board.
The Ethernet signals from the Processor pass through the Main board to the
connector on the rear panel (not shown in the block diagram).
The final sets of signals on the Processor interface are the JTAG chains. There
are two JTAG chains: one to reprogram the Main board PLD and one for the
Channel module PLDs. The chain for the Channel modules goes through a
buffer/multiplexer to allow each module to be accessed independently.
The Processor board has a battery to power the real-time clock. N o other functions
are dependent on the battery. The battery voltage is nominally 3 V and can be
checked from the Diagnostics menu, with threshold levels of >40%, between 20
and 40%, a nd less than 20%.
ECO8000 Series Service Manual 2–5
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