read back the CRC status in 2 different ways:
read the CRC_OK flag in the MSB of the
second byte appended to the RX FIFO after
the packet data. This requires double buffering
of the packet, i.e. the ent
the RX FIFO must be completely read out
before it is possible to check whether the CRC
another solution is to use the
enabled, the entire RX FIFO will be
flushed if the CRC check fails. If
when a sync word is found. The
asserted at the end of the packet. When
the latter occurs the MCU should read the
bytes in the RX FIFO from the
was OK and data can be read out of the FIFO.
by reading the CRC_OK flag
Packet Handling in Transmit Mode
The payload that is to be transmitted must be
written into the TX FIFO. The
must be the length byte when variable packet
length is enabled. The length byte has a value
equal to the payload of the packet (including
the optional address byte).
recognition is enabled on the receiver, the
ten to the TX FIFO must be
the address byte. If fixed packet length is
enabled, then the first byte written to the TX
FIFO should be the address (if the receiver
uses address recognition).
The modulator will first send the programmed
in the TX FIFO, the modulator will send the
then the payload in the TX FIFO. If CRC is
enabled, the checksum is calculated over all
the data pulled from the TX FIFO and the
as two extra bytes following the
payload data. If the TX FIFO runs empty
before the complete packet has been
transmitted, the radio will enter
TXFIFO_UNDERFLOW state. The only way to
exit this state is by issuing an
Writing to the TX FIFO afte
will not restart TX mode.
If whitening is enabled, everything following
the sync words will be whitened. This is done
before the optional FEC/Interleaver stage.
Whitening is enabled by setting
If FEC/Interleaving is enabled, everything
following the sync words will be scrambled by
the interleaver and FEC encoded before being
modulated. FEC is enabled by setting
Packet Handling in Receive
In receive mode, the demodulator and packet
handler will search for a valid preamble and
the sync word. When found, the demodulator
has obtained both bit and byte synchronism
and will receive the first payload byte.
If FEC/Interleaving is enabled, t
decoder will start to decode the first payload
byte. The interleaver will de
before any other processing is done to the
If whitening is enabled, the data will be de
When variable packet length
the first byte is the length byte. The packet
handler stores this value as the packet length
and receives the number of bytes indicated by
the length byte. If fixed packet length
used, the packet handler will accept the
Next, the packet handler optionally checks the
address and only continues the reception if the
address matches. If automatic CRC check is
enabled, the packet handler computes CRC
and matches it with the appended CRC
ayload, the packet handler
will optionally write two extra packet status
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