device data sheet for a complete description. The PMIC voltage domains indicated are for the PDN-0A NVM
configuration.
2. WKUP2 triggers a transition to MCU Only state. LP_WKUP1 and WKUP1 transition to the ACTIVE state
Figure 6-1
Note
The PMIC voltage domain of an IO can be different depending upon configuration. When configured
as an input GPIO3 and GPIO4 are in the VRTC domain. When configured as an output, GPIO3 and
GPIO4 are in the VINT domain.
Note
In addition to the I2C signals, four additional signals are open-drain outputs and require a pullup to a
specific power rail. Please refer to Table 3-2 for a list of the signals and the specific power rail.
Table 3-2. Open-drain signals and Power Rail
PDN Signal Pullup Power Rail
H_MCU_INTn VDD_MCUIO_1V8
H_MCU_PORz_1V8 VDA_MCU_1V8
H_SOC_PORz_1V8 VDA_MCU_1V8
H_DDR_RET_1V1 VDD_DDR_1V1_REG
H_WKUP_I2C0 VDD_MCUIO_3V3
H_MCU_I2C0_SCL/SDA VDD_MCUIO_3V3
Please use Table 3-3as a guide to understand GPIO assignments required for each PDN system feature. If the
feature listed is not required, the digital connection can be removed; however, the GPIO pin is still configured per
NVM defined default function shown. After the processor has booted up, the processor can reconfigure unused
GPIOs to support new functions. GPIO reconfiguration is possible as long as that function is only needed after
boot and default function does not cause any conflicts with normal operations (for example, two outputs driving
same net). For details on how functional safety related connections help achieve functional safety system-level
goals, see Section 4.
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SLVUCJ9 – FEBRUARY 2023
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TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide
for J721S2, PDN-0A
9
Copyright © 2023 Texas Instruments Incorporated
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