VIPA CPU 314ST - Page 156

Byte Bit 7...0
3
n Bit 1 ... 0: Edge selection I+0.3
n Bit 7 ... 2: reserved
4
n Bit 1 ... 0: Edge selection I+0.4
n Bit 7 ... 2: reserved
5
n Bit 1 ... 0: Edge selection I+0.5
n Bit 7 ... 2: reserved
6
n Bit 1 ... 0: Edge selection I+0.6
n Bit 7 ... 2: reserved
7
n Bit 1 ... 0: Edge selection I+0.7
n Bit 7 ... 2: reserved
8
n Bit 1 ... 0: Edge selection I+1.0
n Bit 7 ... 2: reserved
9
n Bit 1 ... 0: Edge selection I+1.1
n Bit 7 ... 2: reserved
10
n Bit 1 ... 0: Edge selection I+1.2
n Bit 7 ... 2: reserved
11
n Bit 1 ... 0: Edge selection I+1.3
n Bit 7 ... 2: reserved
12
n Bit 1 ... 0: Edge selection I+1.4
n Bit 7 ... 2: reserved
13
n Bit 1 ... 0: Edge selection I+1.5
n Bit 7 ... 2: reserved
14
n Bit 1 ... 0: Edge selection I+1.6
n Bit 7 ... 2: reserved
15
n Bit 1 ... 0: Edge selection I+1.7
n Bit 7 ... 2: reserved
n V
ia this record set you may activate a process interrupt for
I+0.0 ... I+1.7 and define for which edge type of the input signal a
process interrupt is thrown.
n Edge selection
– 00b = de-activated
– 01b = Hardware interrupt at edge 0-1
– 10b = Hardware interrupt at edge 1-0
– 11b = Hardware interrupt at edge 0-1 and 1-0
Byte Bit 15...0
0...1
n Input filter I+0.0 in 2.56ms
2...3
n Input filter I+0.1 in 2.56ms
4...5
n Input filter I+0.2 in 2.56ms
6...7
n Input filter I+0.3 in 2.56ms
Record set 81h -
Input filter
VIPA System 300SDeployment I/O periphery
Counter - Parametrization
HB140 | CPU | 314-6CF03 | GB | 16-43 156