Xilinx VCU118 User Manual

VCU118 Board User Guide 34
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Chapter 3: Board Component Descriptions
F26 RLD3_C3_72B_QK6_N DIFF_SSTL12 E6 QK2_B U142
D27 RLD3_C3_72B_QK7_P DIFF_SSTL12 K5 QK3 U142
C28 RLD3_C3_72B_QK7_N DIFF_SSTL12 J6 QK3_B U142
J27 RLD3_C3_72B_QVLD2 DIFF_SSTL12 J12 QVLD0 U142
F25 RLD3_C3_72B_QVLD3 DIFF_SSTL12 J2 QVLD1 U142
A29 RLD3_C3_72B_A0 SSTL12 E2 A0 U141-U142
C29 RLD3_C3_72B_A1 SSTL12 F5 A1 U141-U142
D29 RLD3_C3_72B_A2 SSTL12 F4 A2 U141-U142
B30 RLD3_C3_72B_A3 SSTL12 F9 A3 U141-U142
C30 RLD3_C3_72B_A4 SSTL12 F10 A4 U141-U142
A31 RLD3_C3_72B_A5 SSTL12 F12 A5 U141-U142
A30 RLD3_C3_72B_A6 SSTL12 G3 A6 U141-U142
A33 RLD3_C3_72B_A7 SSTL12 F1 A7 U141-U142
B33 RLD3_C3_72B_A8 SSTL12 G11 A8 U141-U142
B32 RLD3_C3_72B_A9 SSTL12 F13 A9 U141-U142
B31 RLD3_C3_72B_A10 SSTL12 H13 A10 U141-U142
C33 RLD3_C3_72B_A11 SSTL12 D1 A11 U141-U142
C32 RLD3_C3_72B_A12 SSTL12 H11 A12 U141-U142
D30 RLD3_C3_72B_A13 SSTL12 D13 A13 U141-U142
E29 RLD3_C3_72B_A14 SSTL12 H3 A14 U141-U142
F29 RLD3_C3_72B_A15 SSTL12 G2 A15 U141-U142
D32 RLD3_C3_72B_A16 SSTL12 H4 A16 U141-U142
E32 RLD3_C3_72B_A17 SSTL12 H10 A17 U141-U142
D31 RLD3_C3_72B_A18 SSTL12 G12 A18 U141-U142
E31 RLD3_C3_72B_A19 SSTL12 H1 A19 U141-U142
R28 RLD3_C3_72B_A20 SSTL12 F2 NF_A20 U141-U142
E33 RLD3_C3_72B_BA0 SSTL12 G9 BA0 U141-U142
F33 RLD3_C3_72B_BA1 SSTL12 G5 BA1 U141-U142
F30 RLD3_C3_72B_BA2 SSTL12 H8 BA2 U141-U142
G30 RLD3_C3_72B_BA3 SSTL12 H6 BA3 U141-U142
K29 RLD3_C3_72B_WE_B SSTL12 F6 WE_B U141-U142
L30 RLD3_C3_72B_REF_B SSTL12 F8 REF_B U141-U142
H29 RLD3_C3_72B_CK_P SSTL12 H7 CK U141-U142
H30 RLD3_C3_72B_CK_N SSTL12 G7 CK_B U141-U142
Table 3-4: RLD3 Memory 72-bit I/F to FPGA U1 Banks 46, 47, and 48 (Cont’d)
FPGA
(U1) Pin
Schematic Net Name I/O Standard
Component Memory
Pin # Pin Name Ref. Des.
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Xilinx VCU118 Specifications

General

Brand	Xilinx
Model	VCU118
Category	Motherboard
Language	English