Xilinx VCU118

VCU118 Board User Guide 58
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-12: VCU118 FPGA U1 GTY Transceiver Bank 126 Connections
MGT
Bank
FPGA
(U1)
Pin
FPGA (U1) Pin
Name
Schematic Net Name
Connected
Pin
Connected Pin
Name
Connected Device
GTY
Bank
126
T42 MGTYTXP0_126 FMCP_HSPC_DP4_C2M_P A34 DP4_C2M_P
FMC+ HSPC J22
T43 MGTYTXN0_126 FMCP_HSPC_DP4_C2M_N A35 DP4_C2M_N
W45 MGTYRXP0_126 FMCP_HSPC_DP4_M2C_P A14 DP4_M2C_P
W46 MGTYRXN0_126 FMCP_HSPC_DP4_M2C_N A15 DP4_M2C_N
P42 MGTYTXP1_126 FMCP_HSPC_DP5_C2M_P A38 DP5_C2M_P
P43 MGTYTXN1_126 FMCP_HSPC_DP5_C2M_N A39 DP5_C2M_N
U45 MGTYRXP1_126 FMCP_HSPC_DP5_M2C_P A18 DP5_M2C_P
U46 MGTYRXN1_126 FMCP_HSPC_DP5_M2C_N A19 DP5_M2C_N
M42 MGTYTXP2_126 FMCP_HSPC_DP6_C2M_P B36 DP6_C2M_P
M43 MGTYTXN2_126 FMCP_HSPC_DP6_C2M_N B37 DP6_C2M_N
R45 MGTYRXP2_126 FMCP_HSPC_DP6_M2C_P B16 DP6_M2C_P
R46 MGTYRXN2_126 FMCP_HSPC_DP6_M2C_N B17 DP6_M2C_N
K42 MGTYTXP3_126 FMCP_HSPC_DP7_C2M_P B32 DP7_C2M_P
K43 MGTYTXN3_126 FMCP_HSPC_DP7_C2M_N B33 DP7_C2M_N
N45 MGTYRXP3_126 FMCP_HSPC_DP7_M2C_P B12 DP7_M2C_P
N46 MGTYRXN3_126 FMCP_HSPC_DP7_M2C_N B13 DP7_M2C_N
V38 MGTREFCLK0P_126 FMCP_HSPC_GBT0_1_P 3 Q1
U40 ICS85411A
clock buffer
V39 MGTREFCLK0N_126 FMCP_HSPC_GBT0_1_N 4 NQ1
T38 MGTREFCLK1P_126 FMCP_HSPC_GBT1_1_P 8 Q1_P U39 ICS855S006I
clock buffer
T39 MGTREFCLK1N_126 FMCP_HSPC_GBT1_1_N 9 Q1_N
L41 MGTRREF_LN MGTRREF_126 R176.1 100Ω 1% P/U to MGTAVTT_FPGA
L40 MGTAVTTRCAL_LN MGTAVTT_FPGA NA NA NA
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