94 16901A Logic Analysis System Service Guide
8 Theory of Operation
as one large frame. A LAN connection between frames is
used in addition to the multiframe cable for fast data
transfer.
The bus is physically 18 LVDS differential pairs plus ground.
The signals are 100 MHz clock, SYNC, START, eight flags,
RUN, UARTS (receive and transmit), and "cable on"
detection. They route from FPGA to FPGA across frames
with no other hardware other than termination resistors.
The UARTS allow frames to communicate at a low level to
identify themselves and pass IP addressing information. The
"cable on" detection lets the system know when a frame has
been added or removed via power up/down or cable changes.
Together, these functions allow a multiframe setup to
completely self- configure itself and appear as one integrated
measurement system.
Trigg er I N/ OU T These two BNCs function as an external
trigger out and arm in signaling between frames or other
test equipment. The TRIGGER OUT is a simple 3- state
LVTTL 50 Ω line drive circuit. TRIGGER IN (ARM) is
complicated by the need to handle variable threshold levels.
The circuit consists of a programmable 12 bit DAC and
comparator. This combined with a level shift and divide
circuit allows for a ±5 V input range, 200 mV minimum
swing, and 50 mV threshold steps.
Clock IN This BNC input is specifically for a 10 MHz clock
signal from an oscilloscope or other source. The signal is AC
coupled and passed through a 10X multiplier part (low
jitter) and then fed to the FPGA as one of the 100 MHz
clock source choices. Using this input allows two
measurement instruments to run on the same time base and
maintain correct time alignment over long aquisitions.
PLD
The PLD is the low level system control element powered
from the AUX +5 V rail and continuously ON. It logically
controls the soft power ON/OFF through signal lines to the
CPU and power switch monitoring. It physically turns power
ON/OFF via power on/off signals on the power supply sense
cables. In addition to the power switch starting a power
down sequence, two additional monitoring circuits (overtemp
and voltage rail) may cause the PLD to initiate power down.
Both of these conditions are "latched" faults and require
removing the power cord for 15 seconds to clear the
condition.
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