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Chapter 5 Block Diagram
Block Diagram
4
5
Block Diagram
The waveform generator can be divided into four main assemblies: the
processor, the main board, front panel, and the main power supply. A
simplified block diagram is shown on page 136.
The processor is a single board computer and, in addition to the CPU,
contains the RAM, ROM, and circuits used to drive the GPIB, LAN, and
USB ports. The built in web interface is contained in the ROM. The
processor circuitry is earth referenced.
When the power switch is pressed, the processor communicates with and
loads the FPGA. This communication uses three asynchronous serial
data lines and one serial clock line. These four lines are isolated.
The FPGA stores all waveforms except arbitrary waveforms. Arbitrary
waveforms are loaded into SDRAM on the main board. All control of
waveforms, triggers, sync signals, output path, attenuation, and offset is
provided by the FPGA.
The main waveform for each channel is (only a single channel is shown
in the block diagram on page 136) is loaded into the waveform DAC and
clocked by the timebase. The DAC output passes through an elliptical
filter before the main attenuators. There are three attenuators available
in the path, -7.96 dB, -15.91 dB, and -23.87 dB.
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