USB2.0 Data Direction Signal
Part 3.5: Gigabit Ethernet Interface
There are 2 Gigabit Ethernet ports on the AXU2CGB-E carrier board, one
is connected to the PS end, and the other is connected to the PL end. The
GPHY chip uses JLSemi JL2121-N040I Ethernet GPHY chip to provide users
with network communication services. The Ethernet PHY chip on the PS side is
connected to the MIO interface of the BANK502 of the PS side of ZYNQ. The
Ethernet PHY chip on the PL side is connected to the IO of the BANK66. The
JL2121-N040I chip supports 10/100/1000 Mbps network transmission rate, and
communicates with the MAC layer of the ZU2CG system through the RGMII
interface. JL2121-N040I supports MDI/MDX adaptation, various speed
adaptation, Master/Slave adaptation, and MDIO bus for PHY register
management.
When the JL2121-N040I is powered on, it will detect the level status of
some specific IOs to determine its own operating mode. Table 3-5-1 describes
the default settings after the GPHY chip is powered on.
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