Alinx AXU2CGB-E - Part 3.6: USB to Serial Port

AXU2CGB-E User Manual
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Part 3.6: USB to Serial Port
The AXU2CGB-E carrier board is equipped with two Uart to USB ports,
one is connected to the PS end, and one is connected to the PL end.
The conversion chip uses Silicon Labs CP2102GM's USB-UAR chip, and
PHY1_TXCK
PS_MIO64
E19
Ethernet 1 RGMII Transmit Clock
PHY1_TXD0
PS_MIO65
A18
Ethernet 1 Transmit data bit0
PHY1_TXD1
PS_MIO66
G19
Ethernet 1 Transmit data bit1
PHY1_TXD2
PS_MIO67
B18
Ethernet 1 Transmit data bit2
PHY1_TXD3
PS_MIO68
C18
Ethernet 1 Transmit data bit3
PHY1_TXCTL
PS_MIO69
D19
Ethernet 1 Transmit Enable Signal
PHY1_RXCK
PS_MIO70
C19
Ethernet 1 RGMII Receive Clock
PHY1_RXD0
PS_MIO71
B19
Ethernet 1 Receive Data Bit0
PHY1_RXD1
PS_MIO72
G20
Ethernet 1 Receive Data Bit1
PHY1_RXD2
PS_MIO73
G21
Ethernet 1 Receive Data Bit2
PHY1_RXD3
PS_MIO74
D20
Ethernet 1 Receive Data Bit3
PHY1_RXCTL
PS_MIO75
A19
Ethernet 1 Receive Enable Signal
PHY1_MDC
PS_MIO76
B20
Ethernet 1 MDIO Clock Management
PHY1_MDIO
PS_MIO77
F20
Ethernet 1 MDIO Management Data
PHY2_TXCK
B66_L17_N
E8
Ethernet 2 RGMII Transmit Clock
PHY2_TXD0
B66_L18_P
E9
Ethernet 2 Transmit data bit0
PHY2_TXD1
B66_L18_N
D9
Ethernet 2 Transmit data bit1
PHY2_TXD2
B66_L23_P
A9
Ethernet 2 Transmit data bit2
PHY2_TXD3
B66_L23_N
A8
Ethernet 2 Transmit data bit3
PHY2_TXCTL
B66_L24_N
B9
Ethernet 2 Transmit Enable Signal
PHY2_RXCK
B66_L14_P
E5
Ethernet 2 RGMII Receive Clock
PHY2_RXD0
B66_L19_N
A5
Ethernet 2 Receive Data Bit0
PHY2_RXD1
B66_L19_P
B5
Ethernet 2 Receive Data Bit1
PHY2_RXD2
B66_L17_P
F8
Ethernet 2 Receive Data Bit2
PHY2_RXD3
B66_L24_P
C9
Ethernet 2 Receive Data Bit3
PHY2_RXCTL
B66_L22_N
B8
Ethernet 2 Receive Enable Signal
PHY2_MDC
B66_L21_N
A6
Ethernet 2 MDIO Clock Management
PHY2_MDIO
B66_L22_P
C8
Ethernet 2 MDIO Management Data
PHY2_RESET
B66_L14_N
D5
Ethernet 2 Reset Signal