Altera DE2-115 - Clock Circuitry

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HEX7[2]
PIN_AG17
Seven Segment Digit 7[2]
Depending on JP6
HEX7[3]
PIN_AH17
Seven Segment Digit 7[3]
Depending on JP6
HEX7[4]
PIN_AF17
Seven Segment Digit 7[4]
Depending on JP6
HEX7[5]
PIN_AG18
Seven Segment Digit 7[5]
Depending on JP6
HEX7[6]
PIN_AA14
Seven Segment Digit 7[6]
3.3V
4
4
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5
5
C
C
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o
c
c
k
k
C
C
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c
c
u
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t
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r
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y
y
The DE2-115 board includes one oscillator that produces 50 MHz clock signal. A clock buffer is
used to distribute 50 MHz clock signal with low jitter to FPGA. The distributing clock signals are
connected to the FPGA that are used for clocking the user logic. The board also includes two SMA
connectors which can be used to connect an external clock source to the board or to drive a clock
signal out through the SMA connector. In addition, all these clock inputs are connected to the phase
locked loops (PLL) clock input pins of the FPGA to allow users to use these clocks as a source
clock for the PLL circuit.
The clock distribution on the DE2-115 board is shown in Figure 4-11. The associated pin
assignments for clock inputs to FPGA I/O pins are listed in Table 4-5.
Figure 4-11 Block diagram of the clock distribution
Table 4-5 Pin Assignments for Clock Inputs
Signal Name
FPGA Pin No.
Description
I/O Standard
CLOCK_50
PIN_Y2
50 MHz clock input
3.3V
CLOCK2_50
PIN_AG14
50 MHz clock input
3.3V
CLOCK3_50
PIN_AG15
50 MHz clock input
Depending on JP6
SMA_CLKOUT
PIN_AE23
External (SMA) clock output
Depending on JP6
SMA_CLKIN
PIN_AH14
External (SMA) clock input
3.3V