Altera DE2-115 - Page 47

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GND pins. Figure 4-15 shows the I/O distribution of the GPIO connector. The maximum power
consumption of the daughter card that connects to GPIO port is shown in Table 4-10.
Figure 4-15 GPIO Pin Arrangement
Table 4-10 Power Supply of the Expansion Header
Supplied Voltage
Max. Current Limit
5V
1A
3.3V
1.5A
Each pin on the expansion headers is connected to two diodes and a resistor that provides protection
against high and low voltages. Figure 4-16 shows the protection circuitry for only one of the pin on
the header, but this circuitry is included for all 36 data pins.
Figure 4-16 Connections between the GPIO connector and Cyclone IV E FPGA