Altera DE2-115 - Page 60

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ENET1_TX_CLK
PIN_C22
MII transmit clock 2
2.5V
ENET1_TX_DATA[0]
PIN_C25
MII transmit data[0] 2
2.5V
ENET1_TX_DATA[1]
PIN_A26
MII transmit data[1] 2
2.5V
ENET1_TX_DATA[2]
PIN_B26
MII transmit data[2] 2
2.5V
ENET1_TX_DATA[3]
PIN_C26
MII transmit data[3] 2
2.5V
ENET1_TX_EN
PIN_B25
GMII and MII transmit enable 2
2.5V
ENET1_TX_ER
PIN_A25
GMII and MII transmit error 2
2.5V
ENETCLK_25
PIN_A14
Ethernet clock source
3.3V
4
4
.
.
1
1
5
5
T
T
V
V
D
D
e
e
c
c
o
o
d
d
e
e
r
r
The DE2-115 board is equipped with an Analog Device ADV7180 TV decoder chip. The ADV7180
is an integrated video decoder that automatically detects and converts a standard analog baseband
television signals (NTSC, PAL, and SECAM) into 4:2:2 component video data compatible with the
8-bit ITU-R BT.656 interface standard. The ADV7180 is compatible with a broad range of video
devices, including DVD players, tape-based sources, broadcast sources, and security/surveillance
cameras.
The registers in the TV decoder can be programmed by a serial I2C bus, which is connected to the
Cyclone IV E FPGA as indicated in Figure 4-29. Note that the I2C address W/R of the TV decoder
(U6) is 0x40/0x41. The pin assignments are listed in Table 4-24. Detailed information of the
ADV7180 is available on the manufacturer‟s website, or in the DE2_115_datasheets\TV Decoder
folder on the DE2-115 System CD.
Figure 4-29 Connections between FPGA and TV Decoder