Status Byte Register
Status Byte Register reports conditions from the defined status registers,
depending on the bits from the enable registers. So clearing an event register
will clear the coresponding bits from the Status Byte Register.
Bits 0..2 - Not used
- always set to 0
Bit 3 - QUES
- indicates that one or more bits are set in questionable status register
(and the corresponding bits in the enable register are set, too)
Bit 4 - MAV (message available)
- indicates that there is data in the output buffer
Bit 5 - ESB
- indicates that one or more bits sre set in standard event register (and
the corresponding bits in the enable register are set, too)
Bit 6 - RQS
- all the bits from the Status Byte register which have the
corresponding bit from the Status Byte Enable Register set, are
logically Ored. The result is kept in RQS bit.
Bit 7 - Not used
- always set to 0.
Status Byte Register is cleared by:
-
-
*CLS command
-
-
quering Standard Event Register, using *ESR? Command will clear bit 5 in
Status Byte Register
Status Byte Enable Register is cleared by:
-
-
*SRE 0 command