Bridgetek FT801 - Page 40

FT800 Series Programmer Guide
Version 2.1
Document Reference No.: BRT_000030 Clearance No.: BRT#037
40
Product Page
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Register Definition 13 REG_HSYNC1 Definition
31 9 0
Note: NONE
Bit0 - 9: The value of these bits specifies how many PCLK cycles for HSYNC during start of line.
REG_HSYNC1 Definition
R/W
Address: 0x102438
Reset Value: 0x029
Reserved
Register Definition 14 REG_HSYNC0 Definition
31 10 9 0
Note: NONE
Bit0 - 9: The value of these bits specifies how many PCLK cycles of HSYNC high state during
start of line.
R/W
Address: 0x102434
Reset Value: 0x0
Reserved
REG_HSYNC0 Definition