Bridgetek FT801 - Page 78

FT800 Series Programmer Guide
Version 2.1
Document Reference No.: BRT_000030 Clearance No.: BRT#037
78
Product Page
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Register Definition 71 REG_FREQUENCY Definition
31 0
Address: 0x10240C Reset Value: 0x2DC6C00
Read / Write
Bit0 - 31: These bits are set 0x2DC6C00 after reset, i.e. The main clock frequency is 48MHz by
default. The value is in HZ. If the host selects the alternative frequency by using host command
CLK36M, this register must be updated accordingly.
REG_FREQUENCY Definition
Register Definition 72 REG_CLOCK Definition
31 0
Address: 0x102408
Reset Value: 0x00000000
Read Only
Bit0 - 31: These bits are set to zero after reset. The register counts the number of FT800 main
clock cycles since reset. If the FT800 main clock's frequency is 48Mhz, it will wrap around after
about 89 seconds.
REG_CLOCK Definition