Chroma 63200 Series - Standard Event Status; Status Byte Register

High Power DC Electronic Load 63200 Series Operation & Programming Manual
8-4
8.5 Standard Event Status
All programming errors that have occurred will set one or more of the error bits in the
Standard Event Status register.
■ Table 8-2 describes the standard events that apply to the electronic load.
■ Reading of the Standard Event Status register will reset it to zero.
■ The Standard Event Enable register can be programmed to specify the standard event bit
that is logically ORed to become Bit 5 (ESB bit) in the Status Byte register.
Table 8-2 Bit Description of Standard Event Status
Mnemonic
Bit
Value
Meaning
OPC
0 1
Operation Complete. This event bit generated is responding to the
*OPC command. It indicates that the device has completed all
selected pending operations.
QYE
2 4
Query Error. The output queue was read when no data were
present or the data in the queue were lost.
DDE
3
8
Device Dependent Error. Memory was lost, or self-test failed.
EXE
4 16
Execution Error. A command parameter was outside the legal
range or inconsistent with the electronic load’s operation, or the
command could not be executed due to some operating condition.
CME
5 32
Command Error. A syntax or semantic error has occurred, or the
electronic load has received a <GET> within a program message.
8.6 Status Byte Register
■ The Status Byte register summarizes all of the status events from all status registers.
Table 8-3 describes the status events that are applied to the electronic load.
■ The Status Byte register can be read with a serial pull or *STB? query.
■ The RQS bit is the only bit that is automatically cleared after a serial pull.
■ When the Status Byte register is read with a *STB? query, Bit 6 of the Status Byte
register will contain the MSS bit. The MSS bit indicates that the load has at least one
reason for requesting service. *STB? does not affect the status byte.
■ The Status Byte register is cleared by *CLS command.
Table 8-3 Bit Description of Status Byte
Mnemonic
Bit
Value
Meaning
CSUM
2 4
Channel Summary. It indicates if an enabled channel event
has occurred. It is affected by Channel Condition, Channel
Event and Channel Summary Event registers.
QUES
3 8
Questionable. It indicates if an enabled questionable event
has occurred.
MAV
4 16
Message Available. It indicates if the Output Queue contains
data.
ESB
5 32
Event Status Bit. It indicates if an enabled standard event has
occurred.
RQS/MSS
6 64
Request Service/Master Summary Status. During a serial pull,
RQS is returned and cleared. For an *STB? query, MSS is
returned without being cleared.