Chapter 4 System Support
andard ISA interrupts (IRQn).
ndows NT and Windows 2000 operating
The PCI interrupts can be configured by PCI Configuration Registers 60h..63h to share the
st
NOTE: The
systems. Systems running the Windows 95 or 98 operating system will need to run in
8259 mode.
sk e Interrupt processing is controlled and m
ist . These registers are listed in Table 4-9.
9. Maskable Interrupt Contro
Table 4
Maskable Interrupt Control Registers
Register
Base Address, Int. Cn
Initialization Command
APIC mode is supported by the Wi
hrough standard AT-type I/O-mapped
Table 4- l Registers
-9.
Ma abl onitored t
reg ers
I/O Port
020h tlr. 1
021h Word 2-4, Int. Cntlr. 1
0A0h Base Address, Int. Cntlr. 2
1h Initialization Command Word0A 2-4, Int. Cntlr. 2
The initialization and operation of the interrupt control registers follows standard AT-type
protocol.
4.4.1.2
ut may be
maskabl software using logic external to the microprocessor. There are two non-maskable
terrupt signals: the NMI- and the SMI-. These signals have service priority over all maskable
interrupt with the SMI- having top priority over all interrupts including the NMI-.
MI- Generation
he SERR- and PERR- signals are routed through the ICH2 component, which in turn activates
the NMI to the microprocessor.
Non-Maskable Interrupts
Non-maskable interrupts cannot be masked (inhibited) within the microprocessor itself b
e by
in
s,
N
The Non-Maskable Interrupt (NMI-) signal can be generated by one of the following actions:
Parity errors detected on a PCI bus (activating SERR- or PERR-). ♦
♦ Microprocessor internal error (activating IERRA or IERRB)
T
Compaq Evo and Workstation Personal Computers
Featuring the Intel Pentium 4 Processor
Second Edition – January 2003
4-18
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