Technical Reference Guide
The DMA logic is accessed through two types of I/O mapped registers; page registers and
controller registers.
4.4.2.1
s in
plete (24-bit)address for the DMA
Table 4-11.
DMA Page Register Addresses
M I/O Port
DMA Page Registers
The DMA page register contains the eight most significant bits of the 24-bit address and work
onjunction with the DMA controllers to define the comc
channels. Table 4-11 lists the page register port addresses.
Table 4-11. DMA Page Register Addresses
D A Channel Page Register
C ntroller 1 (byte transfers)
o
Ch 0
087h
Ch 1
Ch 2
Ch 3
083h
081h
082h
Controller 2 (word transfers)
Ch 4
n/a
Ch 5
08Bh
Ch 6
Ch 7
089h
08Ah
Refresh 08Fh [see note]
N
The DMA memory page register for the refresh channel must
programmed with 00h for proper operation.
T is derived as follows:
2 ller 1 (Byte Transfers)
OTE:
be
he memory address
4-Bit Address - Contro
-Bit Page Register 8-Bit
23..A16 A15..A0
4-Bit Address - Controller 2 (W
-Bit Page Register 16-Bit D
23..A17
ote that address line A16 from the DM ster is di
ontroller 2 is selected. Address DMA and is 0
y not connecting A00, th
The size of the the bl ed in 1
(words) rather than 8-bits (b
8 DMA Controller
A 0
2 ord Transfers)
8 MA Controller
A A16..A01, (A00 = 0)
N A memory page regi sabled when DMA
c line A00 is not connected to controller 2 always
when word-length transfers are selected.
B e following applies:
♦ ock of data that can be moved or addressed is measur 6-bits
ytes).
♦ The words must always be addressed on an even boundary.
Compaq Evo and Workstation Personal Computers
Featuring the Intel Pentium 4 Processor
Second Edition - January 2003
4-21
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