5.7 Driver Switch Logic Board Adjustments
JP1, a 10–pin header on the Driver Switch Logic board, sets the time between program failure
and carrier disable (automatic turnoff). The times are approximate. Sections 2.11, 2.12, and
4.7 contain further information.
1. Short pins 1 and 2 for a 30 second delay.
2. Short pins 3 and 4 for a 2 minute delay.
3. Short pins 5 and 6 for a 4 minute delay.
4. Short pins 7 and 8 for an 8 minute delay.
5. Short pins 9 and 10 to disable the circuit.
You may select other times by changing the value of R28. The time is proportional to the re-
sistance.
5.8 Bias Set (RF Power Amplifier)
The Bias Set trim pot is located inside the PA module on the input circuit board. Set the trim
pot to its full clock-wise position for near-optimum bias.
5-6 FM600 User’s Manual
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