EKF SC3-LARGO - Read;Clear Status Register 1

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User Guide • SC3-LARGO • CompactPCI

Serial CPU Board • Intel

Core

5xxx Processor

Read/Clear Status Register 1

Write: SMBus Address 0xB2

Read: SMBus Address 0xB3

Bit Description CMD_STAT1

7 WDGARMD

0=Normal operation

1=The watchdog is armed and has to be retriggered within its time-out period

6 WDGRST

0=Normal operation

1=Last system reset may be caused by a watchdog time-out

5 WDGHT

0=Normal operation

1=The watchdog already has elapsed half of its time-out period

4 PF5PS

0=Normal operation

1=Last system reset may be caused by a power failure of the +V5PS voltage regulator

3 PF5S

0=Normal operation

1=Last system reset may be caused by a power failure of the +V5S voltage regulator

2 PF33M

0=Normal operation

1=Last system reset may be caused by a power failure of the +V3.3M voltage regulator

1 PF33A

0=Normal operation

1=Last system reset may be caused by a power failure of the +V3.3A voltage regulator

0 PF33S

0=Normal operation

1=Last system reset may be caused by a power failure of the +V3.3S voltage regulator

Except of WDGHT and WDGARMD the bits in this register are sticky, i.e. their state will be kept even

if a system reset occurs. To clear the bits a write to the register with arbitrary data may be performed.