Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 - Page 107

8 ELECTRICAL CHARACTERISTICS
S1C33L03 PRODUCT PART EPSON A-91
A-1
A-8
EDO DRAM random access cycle (basic cycle)
BCLK
A[23:0]
#RAS
#HCAS/
#LCAS
#RD
D[15:0]
#WE
D[15:0]
RAS1
Data transfer #1
Next data transfer
CAS1 PRE1 (precharge) RAS1' CAS1'
t AD t AD t AD
t CASD2 t CASD1
t RDS2
t ACCE
t RACE
t RDH
t RASD2 t RASD1
t RASW
t RDD3 t RDD1
t RDW2
t WRD3 t WRD1
t WRW2
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;;
;;;;;;;;;;
;;;
;;;
t WDD1 t WDD2
;;;;;
;;;;;
t CASW
t CACE
∗1
∗1 tRDH is measured with respect to the first signal change (negation) of either the #RD or the #RASx signals.
EDO DRAM page access cycle
BCLK
A[23:0]
#RAS
#HCAS/
#LCAS
#RD
D[15:0]
#WE
D[15:0]
RAS1
Data transfer #1 Data transfer #2 Next data transfer
CAS1 CAS2 PRE1(precharge) RAS1'
t AD t AD t AD
t RDS
t ACCE
t RACE
t RASD2 t RASD1
t RDD3 t RDD1
t WRD3 t WRD1
;;;;;;;;;
;;;;;;;;;
;;;;;;;;;;;;;;
;;;;;;;;;;;;;;
;;;;;
;;;;;
;;;;
;;;;
t WDD1 t WDD2 t WDD2
;;;;;
;;;;;
t CACE
t ACCE
t RASW
t RDW2
t CASD2 t CASD1
;;;;
;;;;
t CASW
t WRW2
t RDH t RDS t RDH
∗1
∗1 tRDH is measured with respect to the first signal change from among the #RD (negation), #RASx (negation)
and #CAS (fall) signals.