Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 User Manual

VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
B-VI-2-10 EPSON S1C33L03 FUNCTION PART
Enabling/disabling bank interleaved access
A bank cannot be accessed at the same time it is being precharged, so another bank may be accessed during
that period, which results in increased access speed. For this purpose, the SDRAM controller supports a
feature known as Bank Interleaved Access.
Specify whether or not to use this feature with the SDRBI (D5)/SDRAM advanced control register
(0x39FFC9).
SDRBI = "1": Bank interleaved access function is used
SDRBI = "0": Bank interleaved access function is not used (one bank only is accessed at a time)
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
Bank 1
Bank 2
ACTV
H
NOP NOP NOPACTV READ READ READ
BA1 BA1
ROW2
D(n)
t RRD t RP
(Bank 1 cannot be accessed)
CAS latency
= 2
(CAS latency = 2, t
RCD = 2)
ROW2
ROW1
ROW1
Active
Read Precharge
Active
Read
COLn
BA2
COLm
BA1
COLl
BA2
PRE NOP NOP
BA1
D(m) D(l)
ACTV
BA1
ROW3
ROW3
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
Bank 1
Bank 2
H
NOP NOPACTV READ PRE NOPPRE
BA1 BA1
D(n)
(CAS latency = 2, t RCD = 2)
ROW1
ROW1
ROW2
ROW2
Active
Read Precharge
Active
Read Precharge
COLn
BA1 BA2
ACTV NOP ACTVNOP
BA2
ROW3
ROW3
BA1
D(m)
READ
BA2
CONm
When SDRBI = "0"
When SDRBI = "1"
Figure 2.6 Bank Interleaved Access
When SDRBI is set to "0", the SDRAM controller issues the precharge command every time the bank to be
accessed is changed. This reduces current consumption than that of the bank interleaved access, so set SDRBI
to "0" if bank is hardly changed through a series of access.

Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Specifications

General

Brand	Epson
Model	CMOS 32-Bit Single Chip Microcomputer S1C33L03
Category	Computer Hardware
Language	English