Model 5601ACO2 Automatic Changeover Unit
TECHNICAL DESCRIPTION Revision 1.2 Page 4-11
4.6.4. Show Status
4) Show Status – shows a synopsis of all of the above 3 items, and also shows the status of all input
channels. There are no settable controls under this menu item.
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Trap destinations
Trap Destination 1: 192.168.192.215
Trap Destination 2: 128.0.0.0
Trap Destination 3: 128.0.0.0
Trap Destination 4: 128.0.0.0
Trap Destination 5: 128.0.0.0
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Community Strings
Read-Only: |public|
Read-Write: |private|
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ip address: 192.168.192.154
netmask address: 255.255.192.0
gateway: 192.168.192.10
broadcast address: 255.255.255.255
DHCP enabled: True
Ethernet: enabled
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Individual channel voting enabled.
In voting, I = included, E = excluded.
Sync 1 = I. Sync 2 = I. Sync 3 = I. Sync 4 = I. Sync 5 = I. Sync 6 = I.
LTC 1 = I. LTC 2 = I. GPO 1 = I. GPO 2 = I.
Word Clock = E. Ten MHz = I. ATG 1 = I. ATG 2 = E.
Balanced AES 1 = I. Balanced AES 2 = I. Balanced DARS = I.
Unbalanced AES 1 = I. Unbalanced AES 2 = I. Unbalanced DARS = I.
TG 1-1 = E. TG 1-2 = I. TG 2-1 = I. TG 2-2 = I.
TG 3-1 = I. TG 3-2 = I. TG 4-1 = I. TG 4-2 = I.
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Input status. A = present on input A, a = not present on input A
B = present on input B, b = not present on input B
Sync 1 = ab. Sync 2 = ab. Sync 3 = ab.
Sync 4 = ab. Sync 5 = ab. Sync 6 = ab.
LTC 1 = ab. LTC 2 = ab. GPO 1 = ab. GPO 2 = ab.
Ten MHz = ab. Word Clock = ab. ATG = ab.
Balanced AES1 = ab. Balanced AES2 = ab. Balanced DARS = ab.
Unbalanced AES1 = ab. Unbalanced AES2 = ab. Unbalanced DARS = ab.
Test Gen 1-1 = ab. Test Gen 1-2 = aB. Test Gen 2-1 = ab. Test Gen 2-2 = ab.
Test Gen 3-1 = ab. Test Gen 3-2 = ab. Test Gen 4-1 = ab. Test Gen 4-2 = ab.
Power Supply Left = Failed. Power Supply Right = Ok.
Temperatures (deg C): CPU = 30, FPGA = 49, PS Left unknown, PS Right = 23
Fans: Front Left Fail Rear Left Fail Front Right Ok Rear Right Ok Door is Closed Current output
selected is B
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