as Standard and Allan Deviation on sample
sizes up to 2
*
10
9
.
No Mistakes
You will soon find that your instrument is
more or less self-explanatory with an intuitive
user interface. A menu tree with few levels
makes the timer/counter easy to operate. The
large backlit graphic LCD is the center of in
-
formation and can show you several signal pa
-
rameters at the same time as well as setting
status and operator messages.
Statistics based on measurement samples can
easily be presented as histograms or trend
plots in addition to standard numerical mea
-
surement results like max, min, mean and
standard deviation.
The AUTO function triggers automatically on
any input waveform. A bus-learn mode sim-
plifies GPIB programming. With bus-learn
mode, manual counter settings can be trans-
ferred to the controller for later reprogram-
ming. There is no need to learn code and syn-
tax for each individual counter setting if you
are an occasional bus user.
Design Innovations
State of the Art Technology
Gives Durable Use
These counters are designed for quality and
durability. The design is highly integrated.
The digital counting circuitry consists of just
one custom-developed FPGA and a 32-bit
microcontroller. The high integration and low
component count reduces power consumption
and results in an MTBF of 30,000 hours.
Modern surface-mount technology ensures
high production quality. A rugged mechanical
construction, including a metal cabinet that
withstands mechanical shocks and protects
against EMI, is also a valuable feature.
High Resolution
The use of reciprocal interpolating counting
in this new counter results in excellent relative
resolution: 12 digits/s for all frequencies.
The measurement is synchronized with the in-
put cycles instead of the timebase. Simulta-
neously with the normal “digital” counting,
the counter makes analog measurements of
the time between the start/stop trigger events
and the next following clock pulse. This is
done in four identical circuits by charging an
integrating capacitor with a constant current,
starting at the trigger event. Charging is
stopped at the leading edge of the first follow
-
ing clock pulse. The stored charge in the inte
-
grating capacitor represents the time differ
-
ence between the start trigger event and the
leading edge of the first following clock pulse.
A similar charge integration is made for the
stop trigger event.
When the “digital” part of the measurement is
ready, the stored charges in the capacitors are
Preface 1-3
Preparation for Use
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