Furuno DSC-60 - Page 19

2-9
3. Function and overview of each board
SYN block diagram SYN block diagram SYN block diagram SYN block diagram
SYN block diagram
Q506
Q507
Q509
Q510
Q501
Q511
Q512 Q513
Q508
FL501 SFSH6.0MCB
FL502 SFSH6.0MCB
Q502/503
FL503 CFUM455E
2SD966-Q
U504
AN7812F
1Lo(F+54.455MHz) 2Lo(54MHz) 3Lo(456.7kHz) TEST SIG(18MHz)
TEST
VCO
CLK
CLK
DATA
DATA
ST SYN
DDS CLK
DDS DATA
+15V
OVEN(+24V)
OVEN
+15V(A)
TP501
TP505
TP502
TP503
TP506
DDS3 LOAD
DDS1 LOAD
DDS CLK
DDS DATA
DDS3 LOAD
PLL1 ENB
Ref.OSC (36MHz)
U502 MC145170D2
U501 AD9832BRU
U506 AD9832BRU
U505
PB1509GV
(1/2 DIV)
(DDS)
(DDS)
(PLL)
U503 M54972FP
M CLK
M CLK
Fin
OSCin
36MHz
18MHz
18MHz
54MHz
3SK131
PDout
SinLatch T
Q2
Q1 Q3 Q4 Q5 Q6 Q8Q7
CR510
Q514
SW
Freq. ADJ
PLL1 ENB
T501
T502
T503
T504
H/L
LPF-1 LPF-2
TP501: 1.8Vp-p TP505: 2.0Vp-p