5-38 170 Series Monitor Revision C
2000947-004
Theory of Operation: FECG/IUP Board Theory of Operation
FECG Channel
The input to the FECG channel is two resistors R42 and R43 with the signal names
of RA and LA respectively. Resistors R42, R43, R45, and R462 and capacitors C38
through C40 provide RF filtering, and in conjunction with diode limiters D3 through
D6 provide protection from electro-static discharge. Resistors R40, R41, and R44
cause amplifier U7 to saturate when the FECG cable is not connected to a fetus.
This disables the FECG channel from counting noise and flashing LEDs and causing
tones to be generated by the speaker. Instrumentation amplifier U7 provides a gain
of 13.7 which is given by (49.4E3/R54)+1. Amplifier U2 (pins 5, 6, and 7) is an
integrator which has high gain at DC with reducing gain as frequency increases.
Amplifier U2 (pin 7) drives amplifier U2 (pin8). Amplifier U2 (pin 8) is non-
inverting and is patient protected in the event of a failure of this device. The two
sections of U2 provide the right leg drive circuit. The right leg drive is a feedback
circuit that provides drive in the opposite polarity to a common mode voltage. Its
purpose is to cancel DC offset from the electrode, and to help reject 50 and 60 Hz
components. The output of U7, which is inverting with respect to the signal RA,
drives the non-inverting amplifier U2 (pin 12) through a high-pass filter of 10 Hz.
Resistor R58 and diode D7 provide voltage limiting at U2 (pin 12). This amplifier
has a gain of 22.5 and rolls off at approximately 224 Hz. The output of U2 (pin 14)
drives U8 (pin 3) through R64. Resistor R64 and diode D8 provide voltage limiting
at U8 (pin 3). This amplifier has a gain of 22.5 and rolls off at approximately 224
Hz. The composite bandwidth and gain at this point is from 10 Hz to 320 Hz with a
gain of 6936. The output of U8 (pin 1) drives amplifier U8 (pin 5) with a division of
10/11 formed by resistors R67 and R68. The operation of this amplifier is best
understood if analyzed from its quiesent condition of no input signal. Under this
condition U8 (pin 5) is at zero volts, therefore U8 (pin 6) must also be at zero volts.
This forces a quiesent current of 75 µA through R69. This current is produced by U8
(pin 7) driving the LED that illuminates the photodiode at U11 (pins 3 and 4) which
is the feedback path. The LED also illuminates the photodiode at U11 (pins 5 and 6)
which are on the un-isolated side. The current transfer ratio of this photodiode, with
respect to the photodiode, on U11 (pins 3 and 4) is 0.85 to 1.05. The input voltage
required to drive U8 (pin 1) to either of its power supply limits is approximately
±1.44 mV peak. This corresponds to approximately ±5 V at U8 (pin 1) for ±0.72 mV
input, and ±4.55 V at U8 (pin 5). This causes a delta current of 34.2 µA through
R69, which is also transferred across the barrier with the same transfer ratio of 0.85
to 1.05. This current is input to U15 (pin 3) with resistor R75 being the load resistor
that produces a voltage proportional to the current transferred to it. Amplifier U15
(pin 7) produces an offset voltage of –1.97 V. The quiesent current of 75 µA flowing
through R75 will produce a voltage of approximately +1.25 V at U15 (pin 3). A
0.72 mV signal peak-to-peak at the input will produce approximately 1.26 V at U15
(pin 1). Thus ±1.44 mV at the input will produce ±2.52 V at U15 (pin 8). Amplifier
U15 (pin 14) is a non-inverting amplifier with a gain of one. It also provides 3
sections of high-pass filtering at 25 Hz. Amplifier U15 (pin 8) is a non-inverting
amplifier with a gain of one. It also provides 3 sections of low-pass filtering at 90
Hz.
Mode Enables
The FECG enable ties resistor R87 to the floating ground when the FECG cable is
attached. This causes approximately 4.5 mA to flow in the LED of opto-coupler
U17. The current transfer function of the coupler is 19% typically which causes 860
µA to flow in the photo-transistor of U17 in turn causing R103 to be pulled to
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