Hytera PT580 - Diagram of Reset Signal; Reset Signal; Diagram of CLOCK; Clock

Service Manual
The MCU is connected with a 128Mbits NOR FLASH (for program or data storage) and a 128Mbits
SDRAM (for temporary data storage).
2.2.4 CLOCK
The 32K clock, also called real-time clock (RTC), is used for system starting, timing, sleeping and etc.
The generation of the 9.216MHz clock is controlled by the FPGA. This clock is provided to the baseband
processor.
FPGA
R
9.216_VCO_ON
/VCO_UP
VCO_ DOWN
MCLK
DA
+3V_TCXO
12MHz_REF
PLL
OSCINIF
RF
12MHz
AFC
Synthesizer
12MHz_CLK
CPU
OSC1_IN
OSC1.IN
1V6D
32.768K
12MHz_CLK
9.216M_FPGA
SIM
SIM_CLK
Cartesian
Loop IC
SCLK
BITCLK
SPI.SCK
MCBSP1_ CLKX
MCBSP2_ CLKX
MCBSP3_ CLKX
9.216M_CLK
CLK32_K
IN
CLK
32K
_
SYMCLOCK
CMX_ SCLK
SPI. SCK
SCK
CLK
RF
Baseband
Processor
IO
_L02P
_1/A14
R
Figure 11 Diagram of CLOCK
2.2.5 Reset signal
NOR Flash
PMU
/RESET
/RST-OUT
LCD
CODEC
MCU
RESET-CODEC
/RST-OUT
Figure 12 Diagram of Reset Signal
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