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Intel BX80623I32100 User Manual

Intel BX80623I32100
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Datasheet, Volume 1 29
Interfaces
2.4.1 3D and Video Engines for Graphics Processing
The 3D graphics pipeline architecture simultaneously operates on different primitives or
on different portions of the same primitive. All the cores are fully programmable,
increasing the versatility of the 3D Engine. The Gen 6.0 3D engine provides the
following performance and power-management enhancements:
Up to 12 Execution units (EUs)
•Hierarchal-Z
Video quality enhancements
2.4.1.1 3D Engine Execution Units
Supports up to 12 EUs. The EUs perform 128-bit wide execution per clock.
Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel
processing.
2.4.1.2 3D Pipeline
2.4.1.2.1 Vertex Fetch (VF) Stage
The VF stage executes 3DPRIMITIVE commands. Some enhancements have been
included to better support legacy D3D APIs as well as SGI OpenGL*.
2.4.1.2.2 Vertex Shader (VS) Stage
The VS stage performs shading of vertices output by the VF function. The VS unit
produces an output vertex reference for every input vertex reference received from the
VF unit, in the order received.
2.4.1.2.3 Geometry Shader (GS) Stage
The GS stage receives inputs from the VS stage. Compiled application-provided GS
programs, specifying an algorithm to convert the vertices of an input object into some
output primitives. For example, a GS shader may convert lines of a line strip into
polygons representing a corresponding segment of a blade of grass centered on the
line. Or it could use adjacency information to detect silhouette edges of triangles and
output polygons extruding out from the edges.
2.4.1.2.4 Clip Stage
The Clip stage performs general processing on incoming 3D objects. However, it also
includes specialized logic to perform a Clip Test function on incoming objects. The Clip
Test optimizes generalized 3D Clipping. The Clip unit examines the position of incoming
vertices, and accepts/rejects 3D objects based on its Clip algorithm.
2.4.1.2.5 Strips and Fans (SF) Stage
The SF stage performs setup operations required to rasterize 3D objects. The outputs
from the SF stage to the Windower stage contain implementation-specific information
required for the rasterization of objects and also supports clipping of primitives to some
extent.

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Intel BX80623I32100 Specifications

General IconGeneral
BrandIntel
ModelBX80623I32100
CategoryComputer Hardware
LanguageEnglish

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