Datasheet, Volume 1 27
Interfaces
2.2.4 PCI Express* Lanes Connection
Figure 2-5 demonstrates the PCIe lanes mapping.
2.3 Direct Media Interface (DMI)
Direct Media Interface (DMI) connects the processor and the PCH. Next generation
DMI2 is supported.
Note: Only DMI x4 configuration is supported.
2.3.1 DMI Error Flow
DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or
GPE. Any DMI related SERR activity is associated with Device 0.
2.3.2 Processor / PCH Compatibility Assumptions
The processor is compatible with the Intel
®
6 Series Chipset PCH. The processor is
not compatible with any previous PCH products.
Figure 2-5. PCI Express* Typical Operation 16 lanes Mapping
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1 X 16 Controller
Lane 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 8
Lane 9
Lane 10
Lane 11
Lane 12
Lane 13
Lane 14
Lane 15
0
1
2
3
4
5
6
7
1 X 8 Controller
0
1
2
3
1 X 4 Controller
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