Datasheet, Volume 1 21
Interfaces
2.1.2 System Memory Timing Support
The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
•t
CL
= CAS Latency
•t
RCD
= Activate Command to READ or WRITE Command delay
•t
RP
= PRECHARGE Command Period
• CWL = CAS Write Latency
• Command Signal modes = 1n indicates a new command may be issued every clock
and 2n indicates a new command may be issued every 2 clocks. Command launch
mode programming depends on the transfer rate and memory configuration.
Notes:
1. System memory timing support is based on availability and is subject to change.
2.1.3 System Memory Organization Modes
The IMC supports two memory organization modes—single-channel and dual-channel.
Depending upon how the DIMM Modules are populated in each memory channel, a
number of different configurations can exist.
2.1.3.1 Single-Channel Mode
In this mode, all memory cycles are directed to a single-channel. Single-channel mode
is used when either Channel A or Channel B DIMM connectors are populated in any
order, but not both.
2.1.3.2 Dual-Channel Mode – Intel
®
Flex Memory Technology Mode
The IMC supports Intel Flex Memory Technology Mode. Memory is divided into a
symmetric and an asymmetric zone. The symmetric zone starts at the lowest address
in each channel and is contiguous until the asymmetric zone begins or until the top
address of the channel with the smaller capacity is reached. In this mode, the system
runs with one zone of dual-channel mode and one zone of single-channel mode,
simultaneously, across the whole memory array.
Note: Channels A and B can be mapped for physical channels 0 and 1 respectively or vice
versa; however, channel A size must be greater or equal to channel B size.
Table 2-3. DDR3 System Memory Timing Support
Segment
Transfer
Rate
(MT/s)
tCL
(tCK)
tRCD
(tCK)
tRP
(tCK)
CWL
(tCK) DPC
CMD
Mode
Notes
1
All Desktop
segments
1066
7776
11n/2n
22n
8886
11n/2n
22n
1333 9 9 9 7
11n/2n
22n
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