Power Management
44 Datasheet, Volume 1
4.1 Advanced Configuration and Power Interface
(ACPI) States Supported
The ACPI states supported by the processor are described in this section.
4.1.1 System States
4.1.2 Processor Core / Package Idle States
4.1.3 Integrated Memory Controller States
4.1.4 PCI Express* Link States
Table 4-1. System States
State Description
G0/S0 Full On
G1/S3-Cold Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported by the processor).
G1/S4 Suspend-to-Disk (STD). All power lost (except wakeup on PCH).
G2/S5 Soft off. All power lost (except wakeup on PCH). Total reboot.
G3 Mechanical off. All power removed from system.
Table 4-2. Processor Core / Package State Support
State Description
C0 Active mode, processor executing code
C1 AutoHALT state
C1E AutoHALT state with lowest frequency and voltage operating point
C3
Execution cores in C3 flush their L1 instruction cache, L1 data cache, and L2 cache to the L3
shared cache. Clocks are shut off to each core.
C6 Execution cores in this state save their architectural state before removing core voltage.
Table 4-3. Integrated Memory Controller States
State Description
Power up CKE asserted. Active mode
Pre-charge
Power-down
CKE de-asserted (not self-refresh) with all banks closed
Active Power-
Down
CKE de-asserted (not self-refresh) with minimum one bank active
Self-Refresh CKE de-asserted using device self-refresh
Table 4-4. PCI Express* Link States
State Description
L0 Full on – Active transfer state
L0s First Active Power Management low power state – Low exit latency
L1 Lowest Active Power Management – Longer exit latency
L3 Lowest power state (power-off) – Longest exit latency
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