10-14 Status Structure Model 6487 Reference Manual
• Bit B3, low limit 2 fail (LL2F) — Set bit indicates that the low limit 2 test has
failed.
• Bit B4, high limit 2 fail (HL2F) — Set bit indicates that the high limit 2 test has
failed.
• Bit B5, limits pass (LP) — Set bit indicates that all limit tests passed.
• Bit B6, reading available (RAV) — Set bit indicates that a reading was taken and
processed.
• Bit B7, reading overflow (ROF) — Set bit indicates that the reading exceeds the
selected measurement range of the Model 6487.
• Bit B8, buffer available (BAV) — Set bit indicates that there are at least two
readings in the buffer.
• Bit B9, buffer full (BFL) — Set bit indicates that the buffer is full. This bit will
also be set when a voltage sweep has been completed (Section 6), and if the
programmed number of A-V ohms cycles have been taken (Section 3).
• Bit B10, input overvoltage (IOV) — Set bit indicates there is an input over
voltage condition.
• Bit B11, output interlock asserted (INT) — Set bit indicates that the output
interlock is asserted and the voltage source output cannot be turned on.
• Bit B14, voltage source compliance (VSC) — Set bit indicates that the voltage
source is in compliance.
Questionable event status
The used bits of the questionable event register (Figure 10-7) are described as follows:
• Bit B7, calibration summary (Cal) — Set bit indicates that an invalid calibration
constant was detected during the power-up sequence. This error will clear after
successful calibration of the Model 6487.
• Bit B14, command warning (Warn) — Set bit indicates that a signal oriented
measurement command parameter has been ignored.
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