10-8 Status Structure Model 6487 Reference Manual
The bits of the status byte register are described as follows:
• Bit B0, measurement status (MSB) — Set summary bit indicates that an enabled
measurement event has occurred.
• Bit B1 — Not used.
• Bit B2, error available (EAV) — Set summary bit indicates that an error or status
message is present in the error queue.
• Bit B3, questionable summary bit (QSB) — Set summary bit indicates that an
enabled questionable event has occurred.
• Bit B4, message available (MAV) — Set summary bit indicates that a response
message is present in the output queue.
• Bit B5, event summary bit (ESB) — Set summary bit indicates that an enabled
standard event has occurred.
• Bit B6, request service (RQS)/master summary status (MSS) — Set bit indicates
that an enabled summary bit of the status byte register is set.
• Bit B7, operation summary (OSB) — Set summary bit indicates that an enabled
operation event has occurred.
Depending on how it is used, bit B6 of the status byte register is either the request for ser-
vice (RQS) bit or the master summary status (MSS) bit:
• When using the serial poll sequence of the Model 6487 to obtain the status byte
(a.k.a. serial poll byte), B6 is the RQS bit. See “Serial polling and SRQ,” page 10-9
for details on using the serial poll sequence.
• When using the *STB? command (Table 10-3) to read the status byte, B6 is the
MSS bit.
Service request enable register
The generation of a service request is controlled by the service request enable register.
This register is programmed by you and is used to enable or disable the setting of bit B6
(RQS/MSS) by the status summary message bits (B0, B2, B3, B4, B5, and B7) of the sta-
tus byte register. As shown in Figure 10-3, the summary bits are logically ANDed (&)
with the corresponding enable bits of the service request enable register. When a set (1)
summary bit is ANDed with an enabled (1) bit of the enable register, the logic “1” output
is applied to the input of the OR gate and, therefore, sets the MSS/RQS bit in the status
byte register.
The individual bits of the service request enable register can be set or cleared by using the
*SRE common command. To read the service request enable register, use the *SRE?
query command. The service request enable register clears when power is cycled or a
parameter value of 0 is sent with the *SRE command (i.e. *SRE 0). The commands to pro-
gram and read the SRQ enable register are listed in Table 10-3.
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