201
Pin No Pin Name
BGA QFP
I/O Description
Miscellanous Pins
DISABLE_IFn T8 64 I Interface Disable. When asserted, the interfaces are put
into a Hi-Z state. Interfaces include: ex-CPU, HSDI, GPIO,
and WTCH_DG_TMRn.
HPS P8 62 I Host Power Status. This indicates the power status of the
external system to iceLynx-Micro. A rising edge indicates
the system CPU has been turned ON. (The internal ARM
should wake up.) A falling edge indicates the system CPU
has been turned OFF. (The internal ARM decides if power
down is necessary.)
LOW_PWR_RDY R8 63 O Output to system to indicate iceLynx-Micro is ready to go
into a low power state. The ARM and WTCH_DG_TMRn
control this pin.
WTCH_DG_TMRn U16 88 O Watch Dog Timer (for the ARM.) iceLynx-Micro hardware
asserts this pin whenever ARM software has not updated
the Timer2 register within the allowed time period.
RESET_ARMn U7 60 I ARM reset. This signal resets the internal ARM processor.
RESETn T7 59 I Device reset. This signal resets all logic. This includes the
PHY, Link core, memory, the ARM, and random logic.
Power & Ground Pins
VSS A2,
B1,
B7,
C11,
C16,
G17,
J1,
L15,
P11,
T6
1,
21,
55,
76,
102,
117,
131,
146,
162,
176
Digital Ground.
AGND J2,
K4,
M3,
U2
24,
27,
35,
45,
Analog Ground.
PLL_GND R6 54 PLL Ground.
VDD A7,
B3,
C17,
D3,
D11,
H2,
H15,
L14,
R11,
U6
4,
20,
56,
75,
101,
116,
130,
145,
161,
175
Digital Power Supply. Must be set to 3.3V nominal.
QV01 : TSB43CA42PGF
To Next Page
Loading...
